The ColdFire V4 MCF540X series Integrated ColdFire V4 Microprocessor. Increasing the internal speed of the core allows higher performance and provides system designers with an easy-to-use lower speed system interface. Based on the concept of variable-length RISC technology, the ColdFire family combines the architectural simplicity of conventional 32-bit RISC with a memory-saving, variable-length instruction set. In defining the ColdFire architecture for embedded processing applications, a 68K-code compatible core combines performance advantages of a RISC architecture with the optimum code density of a streamlined, variable-length M68000 instruction set. The MCF5407 is the first standard product to implement the Version 4 ColdFire microprocessor core. The V4 micro architecture implements a number of advanced techniques, including a Harvard memory architecture, branch cache acceleration logic and limited superscalar support (dual-instruction issue).
- ColdFire V4 core-delivering up to 316 (Dhrystone 2.1) MIPS at 220MHz
- Harvard memory architecture and branch cache acceleration logic
- Fully code compatible with V2 and V3 ColdFire cores
- 16kB instruction-cache and 8kB data-cache
- 4kB SRAM
- Multiply-accumulate (MAC) with integer and fractional capabilities
- Hardware integer divide unit
- DRAM controller - Glueless interface to SDRAM or ADRAM
- Two universal asynchronous receiver/transmitter (UARTS), one that supports synchronous operations
- Four fully programmable direct memory access (DMA) channels
- Two 16-bit general-purpose timers
- Parallel I/O interface
- System integration module (SIM)
- 32-bit Internal address bus supporting 4GB of linear address space
- Supervisor/user modes for system protection
- DRAM controller - Up to 512MB of DRAM and support for two separate memory blocks
- Two UARTs - Full-duplex operation, programmable clock and processor-interrupt capability
- Dual 16-bit general-purpose multiple-mode timers
- 16-bit General-purpose I/O interface
- System debug support
计算机和计算机周边
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