The S912ZVHY64F1VLQ is a MagniV mixed signal S12ZVH-family 16-bit Microcontroller The device features a 4x40 liquid crystal display (LCD) controller/driver and a pulse width modulated motor controller (MC) consisting of up to 16 high current outputs. The devices are capable of stepper motor stall detection (SSD) via hardware or software. The MC9S12ZVHY families deliver an optimized solution with the integration of several key system components into a single device, optimizing system architecture and achieving significant PCB space savings. The device also features the revolutionary S12Z CPU with code size and execution efficiencies even higher than our class leading S12X CPU. This also provides a linear memory map for all members of the family, eliminating the inconvenience and performance impact of page swapping. In addition to the I/O ports available in each module, further I/O ports are available with interrupt capability allowing wake-up from stop or wait modes.
Harvard architecture - parallel data and code access
3-Stage pipeline
32-bit Wide instruction and data bus
32-bit ALU
24-bit Addressing (16MB linear address space)
Background debug controller (BDC)
2KB EEPROM with ECC
Phase locked loop (IPLL) frequency multiplier with internal filter
1MHz Internal RC oscillator with +/-1.3% accuracy
4-20MHz Amplitude controlled pierce oscillator
32KHz Oscillator for RTC and LCD
Internal COP (watchdog) module
LCD driver for segment LCD with 40 frontplanes x 4 backplanes
Stepper motor controller (MC) with drivers for up to 2 motors
2 Stepper stall detector (SSD) modules (one for each motor)
RTC support the Hour/Minute/Second function and frequency compensation
ADC with 10-bit resolution and up to 8 channels available on external pins
