The SPC5644AF0MLU1 is a 32-bit Microcontroller based on e200z4 host processor core is built on power architecture technology and designed specifically for embedded applications. In addition to the power architecture technology, this core supports instructions for digital signal processing (DSP). The device has two levels of memory hierarchy consisting of 8kB of instruction cache, backed by 192kB on-chip SRAM and 4MB of internal flash memory. The device includes an external bus interface and also a calibration bus that is only accessible when using the vertical calibration system.
150MHz e200z4 Power Architecture core
Variable length instruction encoding (VLE)
Superscalar architecture with 2 execution units
Up to 2 integer or floating point instructions per cycle
Up to 4 multiply and accumulate operations per cycle
8KB Instruction cache (with line locking), configurable as 2- or 4-way
14 + 3 KB eTPU code and data RAM
5 x 4 Crossbar switch (XBAR)
24 and 16 Entry memory protection unit (MPU)
External bus interface (EBI) with slave and master port
(EN)
