The IS43DR16160A-37CBL is a 256Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls. Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an active command, which is then followed by a read or write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed. The address bits registered coincident with the read or write command are used to select the starting column location (A0-A8 for x16) and (A0-A9 for x8) for the burst access and to determine if the auto pre-charge A10 command is to be issued. Prior to normal operation, the DDR2 SDRAM must be initialized.
- JEDEC standard 1.8V I/O
- Double data rate interface - 2 data transfers per clock cycle
- Differential data strobe
- 4-bit prefetch architecture
- On chip DLL to align DQ and DQS transitions with CK
- 4 Internal banks for concurrent operation
- WRITE latency = READ latency - 1 tCK
- Programmable burst lengths - 4 or 8
- On-die termination (ODT)
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