The LCMXO3L-1300E-5UWG36CTR50 is an ultra-low Density FPGA that supports the most advanced programmable bridging and IO expansion. It has the breakthrough IO density and the lowest cost per IO. The device IO features have the integrated support for latest industry standard IO. It has low power, instant-on, non-volatile PLDs has five devices with densities ranging from 640 to 6900 Look-Up Tables (LUTs). It is designed on a 65nm non-volatile low power process. The device architecture has several features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power for all members of the family.
- High IO/logic, lowest cost/IO, high IO devices for IO expansion applications
- Flexible architecture
- Pre-engineered source synchronous I/O
- High performance, flexible I/O buffer
- I/Os support hot socketing
- Flexible on-chip clocking
- TransFR reconfiguration
- In-field logic update while IO holds system state
- Enhanced system level support
- On-chip oscillator with 5.5% accuracy
- Unique TraceID for system tracking
- Single power supply with extended operating range
- Pin compatible and equivalent timing
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