The DSPIC30F6012A-30I/PF is a 16-bit general purpose Digital Signal Controller with CPU core has a 24-bit instruction word. The Program Counter (PC) is 23-bit wide with the Least Significant bit (LSb) always clear and the Most Significant bit (MSb) is ignored during normal program execution, except for certain specialized instructions. Thus, the PC can address up to 4M instruction words of user program space. An instruction prefetch mechanism is used to help maintain throughput. Program loop constructs, free from loop count management overhead, are supported using the DO and REPEAT instructions, both of which are interruptible at any point.
- Modified Harvard architecture
- C-compiler optimized instruction set architecture
- 84 base instructions with flexible addressing modes
- 24-bit wide instructions, 16-bit wide data path
- 16 x 16-bit working register array modes
- DSP engine - Modulo and bit-reversed addressing modes
- Peripheral features - 3-wire SPI? modules (supports four frame modes)
- 12-bit 200kSPS analogue-to-digital converter (A/D)
- Enhanced flash program memory - 10,000 erase/write cycle (minimum)
- Data EEPROM memory - 100000 erase/write cycle (minimum)
- Self-reprogrammable under software control
- Power-on reset (POR), power-up timer (PWRT) and oscillator start-up timer (OST)
- Flexible Watchdog Timer (WDT) with on-chip low power RC oscillator for reliable operation
- Fail-safe clock monitor operation - Detects clock failure & switches to on-chip LP RC oscillator
- Programmable code protection
- In-Circuit Serial Programming? (ICSP?)
- Programmable brown-out detection and reset generation
- Selectable power management modes - Sleep, idle and alternate clock modes
- Low power, high speed CMOS flash technology
工业, 电源管理, 电机驱动与控制
(EN)
