The MT46V16M16P-5B IT is a 256MB Double Data Rate (DDR) SDRAM uses double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The DDR SDRAM operates from a differential clock (CK and CK#), the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
- Bidirectional data strobe transmitted/received with data, that is source-synchronous data capture
- Internal, pipelined double data rate architecture; two data accesses per clock cycle
- Differential clock inputs
- Commands entered on each positive CK edge
- DLL to align DQ and DQS transitions with CK
- Four internal banks for concurrent operation
- Data mask (DM) for masking write data
- Longer-lead TSOP for improved reliability
- Concurrent auto pre-charge option supported
- RAS lockout supported
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