The MT48LC8M16A2P-6A is a 128MB SDRAM is a high-speed CMOS dynamic Random Access Memory (RAM) containing 134217728-bit. It is internally configured as a quad-bank DRAM with a synchronous interface. Each of the x4s 33554432-bit banks is organized as 4096 rows by 2048 columns by 4-bit. Each of the x8s 33554432-bit banks is organized as 4096 rows by 1024 columns by 8 bits. Each of the x16s 33554432-bit banks is organized as 4096 rows by 512 columns by 16-bit. Read and write accesses to the SDRAM are burst-oriented, accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
- Fully synchronous, all signals registered on positive edge of system clock
- Internal, pipelined operation, column address can be changed every clock cycle
- Internal banks for hiding row access/pre-charge
- Programmable burst lengths - 1, 2, 4, 8 or full page
- Auto pre-charge, includes concurrent auto pre-charge and auto refresh modes
- Self refresh modes - standard and low power
- Auto Refresh - 64ms, 4096-cycle refresh
- LVTTL-compatible inputs and outputs
计算机和计算机周边, 工业, 通信与网络, 消费电子产品
(EN)
