The S25FL512SAGBHI310 is a 512MB MirrorBit? Flash Non-Volatile Memory CMOS 3V core with versatile I/O serial peripheral interface with multi-I/O. Traditional SPI 1-bit serial input and output is supported as well as optional 2-bit and 4-bit serial commands. This multiple width interface is called SPI multi-I/O or MIO. In addition, the FL-S family adds support for double data rate (DDR) read commands for SIO, DIO and QIO that transfer address and read data on both edges of the clock. The eclipse architecture features a page programming buffer that allows up to 256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms. By using FL-S device at the higher clock rates supported, with QIO or DDR-QIO commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories while reducing signal count dramatically.
- SPI Clock polarity and phase modes 0 and 3
- Serial command set and footprint compatible with S25FL-A, S25FL-K and S25FL-P SPI families
- Multi I/O Command set and footprint compatible with S25FL-P SPI family
- Common Flash Interface (CFI) data for configuration information
- Quad-input page programming (QPP) for slow clock systems
- Cycling endurance - 100000 program-erase cycles on any sector typical
- Data retention - 20 years data retention typical
- Status register bits to control protection against program/erase of a contiguous range of sectors
- Advanced sector protection
- Spansion? 65nm MirrorBit technology with Eclipse? Architecture
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