The CD74HC7046AM is a Phase-locked Loop with VCO and lock detector. High-speed silicon-gate CMOS device, specified in compliance with JEDEC Standard No. 7A, are phase-locked-loop (PLL) circuits that contain a linear voltage-controlled oscillator (VCO), two-phase comparators (PC1, PC2) and a lock detector. A signal input and a comparator input are common to each comparator. The lock detector gives a HIGH level at pin 1 (LD) when the PLL is locked. The lock detector capacitor must be connected between pin 15 (CLD) and pin 8 (Gnd). For a frequency range of 100kHz to 10MHz, the lock detector capacitor should be 1000 to 10pF respectively. The signal input can be directly coupled to large voltage signals or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers.
- Excellent VCO frequency linearity
- VCO-inhibit control for ON/OFF keying and for low standby power consumption
- Minimal frequency drift
- Zero voltage offset due to op-amp buffer
- Balanced Propagation Delay and Transition Times
- 10 LSTTL Loads (standard outputs) and 15 LSTTL loads (bus driver outputs) fanout
- NIL = 30%, NIH = 30% of VCC at VCC = 5V High noise immunity
电机驱动与控制, 测试与测量
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