The CDCE906PWG4 is a 3-PLL Programmable Clock Synthesizer/Multiplier/Divider despites its small physical outlines, it is very flexible. It has the capability to produce an almost independent output frequency from a given input frequency. The input frequency can be derived from a LVCMOS, differential input clock or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller. To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-divider and from 1 up to 4095 for the N-divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output. The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (27MHz).
- User programmable PLL frequencies
- EEPROM Programming without the need to apply high programming voltage
- Easy in-circuit programming via SMBus data interface
- Wide PLL divider ratio allows 0ppm output clock error
- Clock inputs accept a crystal or a single-ended LVCMOS or a differential input signal
- LVCMOS Outputs can be programmed for complementary signals
- PLL loop filter components integrated
- Programmable down spread SSC modulation
- Programmable output slew-rate control (SRC) for lowering system EMI
- Development and programming kit for easy PLL design and programming
- Green product and no Sb/Br
时钟与计时
(EN)
