The PC16550DN is an Universal Asynchronous Receiver/Transmitter with FIFOs. It is an improved version of the original 16450 universal asynchronous receiver/transmitter (UART). Functionally identical to the 16450 on power-up (CHARACTER mode: can also be reset to 16450 Mode under software control) the PC16550D can be put into an alternate mode (FIFO mode) to relieve the CPU of excessive software overhead. In this mode internal FIFOs are activated allowing 16 bytes (plus 3-bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes. All the logic is on chip to minimize system overhead and maximize system efficiency. Two pin functions have been changed to allow signalling of DMA transfers. The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM and parallel-to-serial conversion on data characters received from the CPU.
Capable of running all existing 16450 software
After reset, all registers are identical to the 16450 register set
Adds or deletes standard asynchronous communication bits to or from the serial-data stream
Independently controlled transmit, receive, line status and data set interrupts
Independent Receiver Clock Input
MODEM Control functions (CTS, RTS, DSR, DTR, RI and DCD)
Even, odd or no-parity bit generation and detection
False start bit detection
Complete status reporting capabilities
TRI-STATE TTL Drive for the data and control buses
Line break detection and generation
Internal diagnostic capabilities
Loopback controls for communications link fault isolation
Break, parity, overrun and framing-error simulation
(EN)
