The TMS320C6748BZWTD4 is a fixed/floating-point Digital Signal Processor provides significantly lower power than other members of the TMS320C6000? platform of DSPs. The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution. The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a 32kB direct mapped cache and the level 1 data cache is a 32kB 2-way, set-associative cache. The level 2 program cache consists of a 256KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128kB of RAM shared memory.
Dedicated 16-bit time-based counter with period and frequency control
