The TPS51206EVM-745 is an evaluation module for TPS51206. The TPS51206 is a sink/source double data rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low input voltage, low cost, low external component count systems where space is a key consideration. The evaluation module is designed to provide proper termination voltage and a 10mA buffered reference voltage for DDR memory which covers DDR2 (0.9VTT), DDR3 (0.75VTT), DDR3L (0.675VTT) and DDR4 (0.6VTT) specifications with minimal external components.
- VDD voltage: support 5V rail and 3.3V rail
- VLDOIN, VDDQ voltage range: 1.2V to 1.8V
- Build in, onboard transient load to emulate the sink/source transient behavior
- Switch S1, S2 for S3 and S5 Enable function
- Convenient test points for probing VTT, VTTREF, CLK_IN and loop response testing
- Four layer, printed circuit board (PCB) with all the components on the bottom side
电源管理, 嵌入式设计与开发
(EN)
