The SI5326C-C-GM is a jitter-attenuating precision Clock Multiplier for applications requiring sub 1ps jitter performance. The Si5326 accepts two input clocks ranging from 2kHz to 710MHz and generates two output clocks ranging from 2kHz to 945MHz and select frequencies to 1.4GHz. The two outputs are divided down separately from a common source. The Si5326 can also use its crystal oscillator as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range. The Si5326 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5326 is based on silicon laboratories 3rd-generation DSPLL? technology, which provides frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components.
Ultra-low jitter clock outputs with jitter generation as low as 0.3ps rms
Integrated loop filter with selectable loop bandwidth
Meets OC-192 GR-253-CORE jitter specifications
Dual clock inputs with manual or automatically controlled hitless switching
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