The CDCF5801DBQ is a Clock Multiplier/Divider with programmable delay lines down to sub 10ps. It provides clock multiplication from a reference clock (REFCLK) signal with the unique capability to delay or advance the CLKOUT/CLKOUTB with steps of only 1.3-mUI through a phase aligner. For every rising edge on the DLYCTRL pin the CLKOUT is delayed by a 1.3-mUI step size as long as the LEADLAG input detects a low signal at the time of the DLYCTRL rising edge. Similarly for every rising edge on the DLYCTRL pin the CLKOUT is advanced by a 1.3-mUI step size as long as the LEADLAG pin is high during the transition. This unique capability allows the device to phase align (zero delay) between CLKOUT/CLKOUTB and any one other CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG pins. Also it provides the capability to program a fixed delay by providing the proper number of edges on the DLYCTRL pin, while strapping the LEADLAG pin to DC high or low.
Differential/single-ended output
Output can drive LVPECL, LVDS and LVTTL
Three power operating modes to minimize power
No external components required for PLL
Spread spectrum clock tracking ability to reduce EMI (SSC)
Single-ended REFCLK input with adjustable trigger level
(EN)
