The DS90CF364MTD/NOPB is a LVDS Receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 65MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455Mbps per LVDS data channel. Using a 65MHz clock, the data throughput is 170Mbps. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
PLL requires no external components
Falling edge data strobe receiver
Chipset (TX + RX) power consumption of <250mW (typical)
(EN)
